Hierarchical Modelling Concepts

design methodologies

1. top-down: fist define the top level block, then identify the sub-blocks required to create the top level block. we then repeat this for each of the sub-blocks, till they cannot be divided further
2. bottom-up: we build the leaf cells first, then combine them to create higher level blocks.

module

a basic building block in verilog, it provides functionality to higher level blocks via it input and output port interface but hides internal implementation

syntax to create a module

module <module_name> (<module_terminal_list>);
...
<module_internals>
...
endmodule

abstraction

internals of module can be defined in four levels of abstraction, but the module behaves identically with the external environment irrespective of the level of abstraction. the levels are defined below from most to least abstracted:

1. behavioral or algorithmic level: module can be implemented in terms of design algorithm without concerning the hardware implementation details. this is very similar to C programming.
2. dataflow level: module is designed by specifying data flow, the designer is aware of how data flows between hardware registers and how data is processed.
3. gate level: the module is implemented in terms of logic gate and interconnections between the gates.
4. switch level: the module is implemented in terms of switches, storage nodes, and interconnections between them. Verilog allows mixing of all four levels in a design.

instances

modules provide templated which are used to create objects. each object has its own name, variables, paramenters and i/o interface. when a module is invoked, a unique object is created. instantiation is the process of creating objects from module templates.

syntax to create an instance (object) of a module

<module_name> <object_name> (<terminal_list>);

• it is illegal to nest module definitions. that is, every module definition should be global. (like functions in C).

stimulus block

used to check funcitonality of a design block by applying a stimulus and checking results.

• it is a good practice to keep the stimulus block and design block separate.
• the stimulus block is also called a test bench.

two types of stimulus applications are possible

1. first style: the stimulus block instantiates the design block and directly drives the signals in the design block, essentialy becoming the top level block.
2. second style: both the stimulus and design blocks are instantiated in a dummy top level block, and the stimulus interacts with the design block only through the interface.

example: 4 bit ripple carry counter

using top-down design methodology

design blocks

module ripple_carry_counter(q, clk, rst);
	output [3:0] q;
	input clk, rst;

	T_FF tff0(q[0], clk, rst);
	T_FF tff1(q[0], clk, rst);
	T_FF tff2(q[0], clk, rst);
	T_FF tff3(q[0], clk, rst);
endmodule

we created 4 instances of module T_FF (toggle flip flop), hence it must be defined somewhere.

module T_FF(q, clk, rst);
	output q;
	input clk, rst;
	wire d;

	D_FF dff0(q, d, clk, rst);
	not n1(d, q);
endmodule

T_FF instantiates D_FF which uses a not gate for falling edge triggering at d;

module D_FF (q, d, clk, rst);
	output q;
	input d, clk, rst;
	reg q;
	always @(posedge rst or negedge clk)
	if (rst)
		q =1'b0;
	else
		q = d;
endmodule

this defines a D flip flop with synchronous reset. the design block is now complete.

stimulus block

here we control the signals clk and rst and check the 4 bit output q. we use the first style

module stimulus;
	reg clk;
	reg rst;
	wire [3:0] q;

	// instantiate the design block
	ripple_carry_counter r1 (q, clk, rst);

	// control the clock signal that drives the design block. cycle time = 10
	initial
		clk = 1'b0;          // set clock to 0 initially
	always
		#5 clk = ~clk;       // toggle every 5 time units

	// control the reset signal that drives the design block
	// reset is asserted from 0 to 20 and then from 200 to 220
	initial
	begin
		rst = 1'b1;
		#15 rst = 1'b0;
		#180 rst = 1'b1;
		#10 rst = 1'b0;
		#20 $finish;         // terminate the simulaiton
	end

	// monitor the outputs
	initial 
		$monitor ($time, " q = %d", q);
endmodule

Next: [[Basic Verilog Concepts]]